1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to a method and apparatus for transferring semiconductor wafers through a barrier between fabrication areas without transferring, through the barrier, the container which holds the wafers.
2. Description of the Relevant Art
An integrated circuit consists of electronic devices electrically coupled by conducting traces called interconnects. Interconnects are patterned from conducting layers formed on the surface of a semiconductor wafer. The ability to form stacked layers of interconnects has allowed more complex circuits to be implemented in and on relatively small surface areas of silicon substrates. The individual interconnect levels of multilevel interconnect structures are separated by layers of electrically insulating materials (i.e., interlevel dielectric layers).
As the number of interconnect levels is increased, the stacking of additional interconnect layers on top of one another tends to produce greater elevational disparity on the resulting surface topography. Problems of step coverage of a conductive layer upon the rugged topography oftentimes renders trace conductors inoperable or at least unreliable. In additional to step coverage problems, large disparity of the surface topography leads to depth of focus problems when lithography "printing" the conductive film into trace conductors. Abrupt elevational changes in the topography of a semiconductor wafer typically occur at edges of patterned layers such as interconnects. The tendency of layers formed on the surface of a semiconductor wafer to be thinner over steps is called the step coverage problem. A major factor in the processing of integrated circuits with submicron device dimensions is the very small depth of focus of the optical steppers used to pattern circuit features. In order to obtain maximum resolutions, imaging surfaces must be fairly planar with a suitable elevational disparity less than .+-.0.5 microns. Accordingly, interlevel dielectric planarization techniques must be employed in order to make imaging surfaces substantially planar.
Chemical mechanical polish ("CMP") is a popular interlevel dielectric used for its ability to planarize the resulting surface. CMP combines chemical etching and mechanical buffing to remove raised features on a surface of a semiconductor wafer. In a typical CMP process, a semiconductor wafer is mounted on a rotating holder and lowered onto a rotating surface flooded with a mild etchant solution, generally defined as a silica slurry. The etchant grows a thin layer on the exposed wafer surface that is almost simultaneously removed by the buffing action. The net effect is a very controlled polishing process capable of incredible flatness.
One problem with CMP techniques is that they produce large amounts of contaminants, including particulates, metallic ions, and chemical substances. The destructive effects of those contaminants is readily apparent in the overall performance of VLSI or ULSI devices. Any contaminants attributed to the slurry, chemical reactant, or buff/etch byproduct, which is thereafter introduced into other fabrication operations, severely compromises the success of that operation. For example, ingress of contaminants from the CMP operation to the thermal furnaces used for growing oxide, or to the chambers used for implanting ions, would negatively impact the outcome of the grown oxide or junction profile.
Without adequately preventing deposition of CMP-derived contaminants on semiconductor wafers undergoing other fabrication operations, CMP, as an interlevel dielectric planarization method, cannot be successfully used. One way to minimize deposition of CMP-derived contaminants on semiconductor wafers undergoing other fabrication operations (i.e., non-CMP operations) would be to perform the CMP process in an area hermetically sealed from other fabrication areas. Maintaining separate the CMP area from the other fabrication areas begins by installing a wall between those areas. Wafers must, however, be transported between the respective areas so that CMP can be incorporated within the process flow.
Transport of wafers between CMP and non-CMP areas entails passing the wafers through a door separating the areas. The door, depending upon sophistication, can be a load lock chamber adapted for receiving therethrough a wafer-containing boat. The wafer or wafers are transported in the boat through the chamber from one area to another area. The load lock comprises an air circulation and filtration system which effectively flushes the ambient air surrounding the wafers. Unfortunately, however, the load lock by itself cannot in most instances flush contaminants from the surface of boats which contain wafers. The wafer containers, or boats, pick up contaminants while in the CMP fabrication area. When the boats are passed through the load lock unit, those contaminants are not always removed from the boats. As such, the boats being passed from one area to another will maintain inappropriate contaminant count, wherein the contaminants will spread onto the wafers.
It is therefore desirable to minimize the opportunity for a contaminanted boat from passing to and from a CMP area. An effective method of preventing passage of boat-entrained contaminants into what should be a "clean room" environment from a relatively dirty CMP room is to pass only wafers, and not the boats into which they reside, between the fabrication areas. It would also be desirable to have a method of transferring semiconductor wafers between a wall separating a lower contaminant area and a higher contaminant area. To optimally restrict inappropriate movement of contaminants, the transfer must involve passage of semiconductor wafers only, and not the boats used to hold those wafers.